Do you have an IC (fewer than 100,000,000 transistors*) for which you are struggling to bring the parametric yield to 100% without significantly increasing design time and/or transistor area ?
Do you have an IC (fewer than 10,000,000 transistors*) for which you are struggling to bring the parametric yield to 100% without significantly increasing design time and/or transistor area ?
Do you have an IC chip for which you are struggling to bring the parametric yield to 100% without significantly increasing design time and/or transistor area ?
Do you have an IC (fewer than 1,000,000 transistors*) for which you are struggling to bring the parametric yield to 100% without significantly increasing design time and/or transistor area ?
Do you have an IC (fewer than 100,000 transistors*) for which you are struggling to bring the parametric yield to 100% without significantly increasing design time and/or transistor area ?